STA Static Timing Analysis Engineer

Job Description

One of our client is looking for an experienced STA Engineer with 3+ years of hands-on expertise in Static Timing Analysis for complex semiconductor designs. The ideal candidate will have a strong background in timing analysis, closure techniques, and experience with advanced technology nodes.

Key Responsibilities:

• Perform Static Timing Analysis (STA) for digital designs at block, full-chip, and SoC levels.

• Analyze and resolve timing violations through logic and layout modifications.

• Collaborate with physical design, synthesis, and RTL teams to achieve timing closure.

• Work with multi-corner, multi-mode (MCMM) scenarios to ensure timing signoff.

• Utilize industry-standard STA tools such as PrimeTime, Tempus, or ETS.

• Develop and maintain timing constraints (SDC) for synthesis and place & route.

• Support signoff methodologies, including timing ECO (Engineering Change Orders).

• Work on timing models and guide IP integration and timing closure.

• Optimize timing paths and apply techniques like clock gating, retiming, and multi-voltage design.

• Troubleshoot and resolve issues related to setup, hold, and cross-talk timing violations.

Required Skills:

• Strong understanding of digital design fundamentals, timing concepts, and STA methodologies.

• Proficiency in STA tools such as Synopsys PrimeTime, Cadence Tempus, or Mentor Graphics.

• Experience with advanced process nodes (16nm, 7nm, 5nm, etc.).

• Familiarity with timing closure strategies at various stages of the design cycle (pre-layout, post-layout).

• Working knowledge of physical design flows including synthesis, placement, routing, and sign-off.

• Expertise in SDC (Synopsys Design Constraints) development and management.

• Solid understanding of RC extraction, delay calculation, and SI (Signal Integrity) effects.

• Good scripting skills (TCL, Perl, Python) for automating STA tasks.

Preferred Qualifications:

• Experience in handling full-chip STA and SoC-level timing analysis.

• Knowledge of low-power design techniques (multi-voltage, clock gating, etc.).

• Excellent problem-solving skills and ability to work in a collaborative environment.

• Strong verbal and written communication skills.

Educational Qualification:

• B.Tech in Electronics Engineering, Electrical Engineering, or a related field. Benefits:

• Competitive salary and performance-based bonuses

• Comprehensive benefits package, including health insurance, retirement plans, and paid time off

• Opportunities for professional development and career growth

• Collaborative and innovative work environment with state-of-the-art facility